Copper is replacing aluminum as the favored metallization for forming advanced integrated circuits. The copper is used not only for the horizontal wiring patterns in multiple wiring levels but also for the vertical connections between wiring levels. An inter-level via structure is illustrated in the cross-sectional view of FIG. 1. A conductive feature 12, typically of copper, is formed in the surface of a lower level dielectric layer 14, typically of silica or other silicate glass although low-k dielectrics of differing compositions have been proposed. An upper level dielectric layer 16 is deposited over the lower-level dielectric layer 14 and its included conductive feature 12. The dielectric layer 16 typically has a thickness of about 1 μm, and it is not anticipated that the thickness can be reduced beyond about 0.7 μm because of dielectric breakdown and inter-level cross talk. A via hole 18 is etched through the upper level dielectric layer 16 to the underlying conductive feature 12. The figure is simplified and does not show etch stop layers and other features well known in the art but not directly pertinent to the invention.
A thin barrier layer 20 is deposited to form not only a blanket portion over the top of the dielectric layer 16 but also a sidewall portion 22 and a bottom portion 24 in the via hole 18. For copper metallization, the barrier layer 20 is typically composed of a bilayer of Ta/TaN, although other refractory metals and their nitrides are being considered. Sometimes, the bottom portion 24 of the barrier layer 20 is removed to reduce the via contact resistance. The barrier layer 20 performs a number of functions and is accordingly often referred to as a barrier/liner. It provides adhesion to the oxide dielectric layer 16 which does not bond well with copper. It acts as a barrier to prevent the copper from diffusing into the dielectric layer 16, which can short out the dielectric, and to prevent oxygen from diffusing from the oxide dielectric layer 16 into the copper metallization, which would degrade the copper conductivity. It also bonds to the after deposited copper.
A thin copper seed layer 26 is deposited over the barrier layer 20 and serves as a nucleation layer and a plating electrode for a thick ECP copper layer 28 deposited by electrochemical plating (ECP). Although the step is not illustrated, chemical mechanical polishing (CMP) removes the ECP copper layer 28 from the top surface leaving the ECP copper in the via hole 18. In an unillustrated dual damascene process, a vertically extending via hole at the bottom of the upper dielectric layer 16 is connected to a horizontally extending trench at the top of the upper dielectric layer 16. The barrier and copper seed layers 20, 26 are also coated onto the sides of the trench, and the ECP copper layer 28 is filled into both the via hole 18 and the trench, thereby simultaneously forming the vertical via and the horizontal wiring pattern. The conductive feature 12 may be part of a trench of the lower dielectric layer 14.
A somewhat similar structure may be used to form a contact to an underlying silicon circuit although additional contact layers are needed for the interface between the copper and the semiconducting silicon.
Sputtering, alternatively called physical vapor deposition (PVD), may be used to deposit both the barrier layer 22 and the copper seed layer 26. The nitride portion of the barrier layer 22 may be formed by reactive sputtering in which nitrogen gas is introduced into the sputter reactor which reacts with the sputtered refractory metal atoms to deposit a refractory metal nitride on the wafer. However, as the minimum feature width of advanced integrated circuits is being pushed to 0.13 μm and even lower, the aspect ratio of the via hole, that is, the ratio of its depth to its width, has increased to 5 and higher, a difficult geometry for sputtering. To obtain good sidewall and bottom coverage in the via hole 18 requires some advanced sputtering techniques including DC biasing of the wafer and production of a large ionization fraction of the sputtered metal atoms so that the accelerated metal ions are attracted deep within the via hole 18. Fu et al. describe a sputter reactor usable for this purpose in U.S. Pat. No. 6,290,825, incorporated herein by reference in its entirety. In a process called self-ionized plasma (SIP) sputtering, a small unbalanced magnetron is composed of a strong outer pole surrounding an inner pole of lesser magnetic intensity. Because it is small, it is rotated about the back of the target to provide uniform sputtering. A large amount of power is applied to the target and the small magnetron increases the effective power density near the magnetron to thereby increase the plasma density to such an extent that a substantial fraction of the sputtered atoms are ionized. The negatively biased wafer accelerates the positively charged metal ions deep within the high aspect-ratio holes.
It is also possible to deposit the copper seed layer 26 by chemical vapor deposition (CVD), which is better adapted for coating a conformal layer even into high aspect-ratio holes, but sputtering is preferred for economic reasons. The barrier layer 22 or some of its sub-layers may also be deposited by CVD.
Especially for very narrow via holes, the barrier layer 20 should be made as thin as possible. Excess width of the barrier sidewall portion 22 decreases the cross section of the copper conductive filling the remainder of the via hole 18, thus increasing the via resistance. If the barrier bottom portion 24 is not removed, an excessively thick bottom portion 24 also increases the via resistance since the barrier materials are not good conductors. However, the barrier thickness needs to be large enough to guarantee the barrier layer 22 is not formed with pin holes or localized areas that are so thin that they do not serve as an adequate barrier.
Atomic layer deposition (ALD) is a CVD technique that has been developed to deposit very thin metal nitride layers. In ALD, the composition of the feed gas is alternated to permit the deposition of a monolayer of the metal followed by a monolayer of nitrogen. Thereby, the barrier material is deposited one atomic layer at a time, and a few atomic layers have been observed to be sufficient to form an adequate barrier layer. However, ALD tantalum nitride has been observed to have properties differing significantly from PVD tantalum nitride. The ALD form has a higher electrical resistivity and bonds much more poorly with the copper. Furthermore, ALD is not readily usable to form a metallic tantalum layer, which has the advantage of bonding fairly well with the silicate dielectric.
Ding et al. in U.S. Pat. No. 6,387,805 have suggested dispensing with the nitride barrier layer and instead doping the copper seed layer with magnesium, aluminum, or one of a few other metals which form stable oxides at the interface with the silicate dielectric, thereby acting as a barrier layer. It is not clear, however, that the suggested dopants provide adequate bonding to the dielectric.
Several others have suggested doping the copper seed layer with at least one dopant. Their reasons range from preventing agglomeration, reducing electromigration, adhesion, and general surface properties.
We believe that these suggestions in the prior art are insufficient in determining a reasonable dopant contribution in copper seed layers grown in a commercial environment.